The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to a method of forming a self-aligned well implant in transistor devices for improving short channel effects (SCE) control, parasitic capacitance, and junction leakage.
When the channel length of a transistor is scaled down below about 40 nanometers (nm), high well doping is needed to avoid source/drain punchthrough problems. Typically, this type of well implant procedure is carried out prior to gate patterning. As a result, the heavily doped well region is not only located beneath the channel, it is also present in the source/drain regions. In bulk (e.g., silicon) devices, this heavily doped well structure located under the source/drain region increases both junction capacitance and junction leakage. On the other hand, for partially depleted silicon-on-insulator (SOI) devices, the source/drain junctions cannot butt to the buried oxide due to the presence of the heavy well, and thus junction capacitance and leakage will be increased for these devices also.
One solution to this issue may be to increase the source/drain implant energy and dose to facilitate better butting of the source/drain regions to the buried oxide. However, this is not a very efficient approach for scaled devices due to penetration problems. That is, source/drain implant dopants get into the channel through the gates. Another approach could be to add a source/drain tail implant to a graded source/drain profile. Since this entails a larger energy implant, it is also easy to create an undesired, deep source/drain punchthrough condition.